During the formation of a semiconductor device such as memory devices, logic devices, microprocessors, etc., several photolithography steps are typically required. Each photolithography step includes the formation of a blanket photoresist (resist) layer, exposing portions of the resist layer to light using a mask or reticle, removing the exposed resist portions (or the unexposed resist portions if negative resist is used), etching the underlying layer using the resist as a pattern, then stripping the resist.
Another layer related to photolithography is the formation of a hard mask. A hard mask is formed as a blanket layer over the layer to be etched. The patterned resist layer is formed over the hard mask, then the hard mask is etched using the resist as a pattern. After patterning the hard mask, the resist can be removed, or it may remain in place. If the resist is removed the hard mask is the sole pattern for etching the underlying layer; otherwise, the hard mask provides a more robust mask than the resist alone if the resist should be completely eroded away, thereby avoiding the removal of any portion of the underlying layer which is to remain. Etching with the photoresist in place may result in organic resin deposits which can be detrimental, but may also aid in reducing lateral etching of the layer to be etched by depositing polymers along sidewalls of the opening being etched in the underlying layer. While a hard mask requires a separate layer to be formed, etched, and removed, and therefore adds production costs, it is often used because it provides improved resistance to the etch and, overall, reduces costs.
Semiconductor engineers are continually striving to develop hard masks which have improved resistance to an etch when compared with underlying layers. The improved selectivity allows for thinner hard masks, which require less time to be formed and removed, decreases the aspect ratio of the etch, and decreases costs when compared with a thicker hard mask layer.
A material which is presently used as a hard mask includes amorphous carbon (a-C). When etching oxide using a-C as a hard mask, the etch removes the oxide about 10 times faster than it removes the a-C, thereby providing a 10:1 oxide to a-C etch rate.
Present designs of semiconductor devices have aspect ratios which can approach, and may in fact exceed, 10:1 (i.e. the depth of the opening is 10 times greater than the diameter of the opening). To etch this deeply relative to the diameter of the opening requires a long etch time, and therefore a thick hard mask. Amorphous carbon is a translucent material, and as the thickness of the hard mask increases there is increased difficulty in reading alignment or “combi” marks on the semiconductor wafer. Further, increasing the thickness of the hard mask layer requires increasing the deposition time, which increases costs.
A new method for increasing the etch resistance of a-C during the etch of an oxide layer, and the resulting new a-C hard mask, would be desirable.